Chip Engineer - Agentic Frameworks

Job Title: Chip Engineer - Agentic Frameworks
Job ID: 85753
Location: Redwood, California 

What you will be doing:
Domain Knowledge & Tool Enablement

• Encode chip-design expertise (RTL/DV best practices, microarchitectural patterns, failure modes) into reusable, agent-consumable knowledge and playbooks.

• Define EDA tool usage for agents when to run simulation, lint, CDC, synthesis, and STA, how to interpret results, and how to chain tools into reliable flows.

Agent Workflow & Orchestration

• Design end-to-end agent workflows for chip design, verification, debugging, and iterative refinement using structured process graphs.

• Decompose complex silicon workflows into executable agent steps with clear inputs, outputs, and success criteria, including hierarchical and iterative patterns.

Prompt Engineering & Agent Behavior

• Develop high-quality prompts covering specification, microarchitecture, RTL, verification, and debug.

• Define agent behavior models, guardrails, and few-shot examples that guide reasoning, assumption validation, and error handling in chip-design tasks

What you must have:

• 10+ years of experience (Staff) OR 6+ years of experience (Senior) across key domains: Chip Design & Verification

• Digital IC, ASIC, or SoC design or verification, with strong hands-on expertise in SystemVerilog RTL and UVM. Deep familiarity with lint, CDC/RDC, simulation, timing constraints, and STA, and a solid understanding of microarchitecture (pipelines, FIFOs, DMA, caches, interconnects).

• Ability to clearly explain design tradeoffs and debugging strategies.

Salary/Rate Range: $200.00 - $300.00


Thank you for your interest in this opportunity. If you are selected to move forward in the process, we will contact you directly. If you do not hear from us, we encourage you to continue visiting our website for other roles that may be a good fit.


For more information about TEEMA and to consider other career opportunities, please visit our website at www.teemagroup.com